Certain memory cells, including flash memory cells, include at least one floating gate that is/are programmed and erased through one or more program/erase gates, word lines, or other conductive element(s). Some memory cells use a common program/erase gate extending over a floating gate to both program and erase the cell. In some implementations, the floating gate is formed by a Poly1 layer, while the program/erase gate is formed by a Poly2 layer that partially overlaps the underlying Poly1 floating gate in the lateral direction.
FIG. 1 illustrates a partial cross-sectional view of an example memory cell 10A including a Poly 1 floating gate 14 and overlying “football” oxide 16 formed over a substrate 12, and Poly2 common program/erase gate 18 extending partially over the floating gate 14. A distance of lateral overlap between the program/erase gate 18 and underlying floating gate 14, also referred to as the P1/P2 overlap distance or “FG overlap distance,” is indicated in FIG. 1.
The FG overlap distance typically affects both the program and erase characteristics of the cell, including the program and erase current for the cell. In particular, programming efficiency (e.g., lower current) is improved by a smaller FG overlap distance, while erase efficiency (e.g., higher current) is improved by a larger FG overlap distance. Typically, increasing the difference between the erase state current (Ir1) and program state current (Ir0) increases the cell performance/efficiency, and vice versa.
Thus, the erase and program efficiency are antagonistic, and may define a relatively small window for FG overlap distance that provides and effective or desirable difference between program and erase state currents (Ir1/Ir0 difference). Further, the Ir1/Ir0 window is reduced with reduced cell size, due to higher program and erase voltages required in smaller cells, which limits scaling of certain memory cells.
In addition, in cells that include multiple floating gates, e.g., mirrored dual-bitcell flash memory cells, the FG overlap distance may be asymmetrical between the different floating gates due to inherent alignment imperfections or tolerances associated with manufacturing, which may be disadvantageous.
FIG. 2 illustrates an example of a mirrored memory cell 10B (e.g., a SuperFlash cell) including two spaced-apart floating gates 14 with a respective program/erase gate 18 formed over each floating gate 14.
FIG. 3 illustrates another example mirrored memory cell 10C (e.g., a SuperFlash cell) including two spaced-apart floating gates 14, a word line 20 formed over each floating gate 14, and a common erase gate or “coupling gate” 22 formed between and extending over both floating gates 14, such that for each floating gate 14, the program and erase couplings to the respective floating gate 14 are decoupled.